TransEDA Accelerates SOC Verification With Industry's First Emulation Coverage Solution

Introducing New VN-Cover Emulator

LOS GATOS, Calif.--(BUSINESS WIRE)--April 8, 2002--TransEDA® PLC, the leader in ready-to-use verification solutions for electronic designs, announced VN-Cover(TM) Emulator, a new option to its industry-leading VN-Cover coverage analysis solution. VN-Cover Emulator is the industry"s first coverage solution for emulators, providing a seamless coverage environment between simulation and emulation.

With verification dominating IC development schedules and resources, companies need an integrated verification strategy to consistently get new products to market on time. Many companies -- especially those in networking, telecommunications, graphics, and digital signal processing -- have been adopting hardware emulators as part of their strategy to accelerate verification schedules.

Crucial to completing the verification process is measuring which parts of the design have been adequately verified and which areas may require additional attention. VN-Cover Emulator enables customers to collect valuable coverage data on their tests even when using an emulator, and users can seamlessly combine emulation and simulation coverage results for a unified picture of verification completeness. VN-Cover Emulator provides for the first time an objective measure of how well a design has been emulated and which parts of a design have been under-emulated, enabling engineers to release designs sooner with less risk of missing critical design errors.

"Our customers have demanded a unified coverage environment between simulation and emulation,"" said Tom Borgstrom, vice president of marketing, TransEDA. "Because every minute of emulation time is critical, customers are constantly looking for ways to complete emulation sooner. VN-Cover Emulator is a powerful productivity aid, providing objective, quantitative feedback that enables the emulator user to stop emulating sooner with more confidence of first-pass silicon success.""

"We rely on the high performance of emulation to speed the application of random tests on our designs,"" said Anthony Gold, vice president of engineering, Unisys. "Unisys makes extensive use of hardware emulators in the verification of our complex ASIC server chipset designs. With the availability of the TransEDA coverage tool in this environment, we expect to see a significant reduction in ASIC design verification times with fewer design escapes found in silicon. TransEDA"s quantitative coverage feedback helps us determine the optimum schedule release of the design to fab. With the use of additional tools such as VN-Cover for simulation-based coverage, we now have a complete, seamless coverage environment between simulation and emulation that helps speed verification analysis even more.""

"Our customers are facing increased pressure to get products out the door in less time than ever before,"" said Steve Wang, vice president of marketing, Axis Systems. "Adding TransEDA"s coverage support for our Xcite(TM) and Xtreme(TM) simulation acceleration and emulation systems enables our customers to accelerate their code coverage analysis. This increases their verification confidence and speeds time to market.""

"Adding coverage support from TransEDA to our VStation(TM) Emulator means dramatically increased verification productivity for our customers,"" said Linda Prowse Fosler, vice president of marketing, IKOS Systems. "We have strong demand for an emulation coverage solution from our customers. Now they can determine which areas of their design have been fully verified and which need additional attention.""

VN-Cover Emulation Accelerates Verification with Complete Coverage

Support for Leading Emulators: The VN-Cover Emulator option provides optimized coverage support for the Quickturn CoBALT(TM) and CoBALT Plus(TM) platforms from Cadence Design Systems, the IKOS VStation Emulator and Axis Systems Xcite and Xtreme verification systems. Future versions are planned with support for other hardware-assisted verification platforms.

Support for All Emulation Modes: Full support (where applicable) for accelerated co-simulation, synthesizable test bench, in-circuit emulation, ICE-tracer, vector regression, and multi-user operation.

Optimized Instrumentation, Smooth Design Flow: Synthesizable instrumentation tuned for hardware platforms ensures a smooth design flow into and out of emulation.

Objective Measure of Verification Progress: VN-Cover provides an objective measure of how completely a design has been verified -- useful in assessing the thoroughness of an emulation strategy and establishing confidence in design quality.

Quick Identification of Verification Holes: VN-Cover"s results navigation, including worst instance to best instance analysis, enables quick identification of areas that need additional testing, as well as thorough assessment of the verification plan.

Seamless Integration Between Simulation and Emulation: VN-Cover merges results from multiple emulation runs and from emulator and simulation runs, giving a complete picture of the verification effort. Results can be marked so un-verifiable areas do not affect coverage results, providing documentation of coverage exceptions and accurate coverage results.

Meaningful Results: VN-Cover Emulator provides complete and objective statement coverage for the identification of dead code, branch coverage for the identification of control logic errors, and toggle coverage to highlight problems with signal controllability.

About Verification Navigator

VN-Cover Emulator is available as part of the TransEDA Verification Navigator® integrated design verification environment. In addition to coverage analysis for simulation and emulation, Verification Navigator includes VN-Property DX(TM) Dynamic Property Checking, VN-Control(TM) Application Specific Test Automation, VN-Check(TM) Configurable HDL Checking, and VN-Optimize(TM) Test Suite Analysis.

Pricing and Availability

VN-Cover Emulator is available immediately for Quickturn CoBALT and CoBALT Plus hardware platforms from Cadence Design Systems and on the Axis Xcite and Xtreme verification systems. Support for the IKOS VStation platform will be available in the second half of 2002. Pricing starts at $50,000 (U.S.) for an annual subscription license. For more information on the VN-Cover Emulator option, visit the TransEDA Web site at www.transeda.com or email info@transeda.com.

About TransEDA

TransEDA PLC (symbol TRA on the Alternative Investment Market in London) develops and markets ready-to-use verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs.

The company"s verification IP library includes models and properties for advanced microprocessors and bus interfaces. TransEDA"s design verification software performs application-specific test automation, configurable HDL checking; code and finite state machine (FSM) coverage analysis, dynamic property checking, and test suite analysis.

TransEDA"s tier-1 list of customers includes 18 of the world"s top 20 semiconductor vendors. For more information, visit www.transeda.com or contact TransEDA at 983 University Avenue, Building C, Los Gatos, California 95032 U.S.A., telephone 408/335-1300, fax 408/335-1319, email info@transeda.com.

Note to Editors: TransEDA and Verification Navigator are registered trademarks and Foundation Models, VN-Cover, VN-Check, VN-Control, VN-Property DX, and VN-Optimize are trademarks of TransEDA. All other trademarks are properties of their respective holders.

     TransEDA
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     tom.borgstrom@transeda.com
         or
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     jen@akipr.com
         or
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         or
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